A conventional processor can receive an interrupt at the same time that it is servicing another interrupt. Consider a situation where a processor is executing a thread of instructions when a first interrupt occurs. The state of the conventional processor (including status flag information and a program counter value) is pushed onto a stack, maskable interrupts are disabled, and the processor vectors off to a first interrupt service routine for handling the first interrupt. If the conventional processor were to complete execution of the first interrupt service routine, then the processor would encounter an interrupt return instruction at the end of the interrupt service routine. Execution of this interrupt return instruction would cause the state of the processor that was previously pushed onto the stack to be popped off. The recovered state information would then be used to restore the processor to the state it was in when the processor vectored off to the first interrupt service routine. After the state was restored, the processor could continue executing the thread of instructions as if the first interrupt had never occurred.
Consider next a situation where a second interrupt (a maskable interrupt) occurs during the conventional processor's execution of the first interrupt service routine. The second interrupt is not serviced because maskable interrupts are automatically disabled during execution of the first interrupt service routine. The maskable interrupt is therefore pending but is not serviced. When the processor encounters the interrupt return instruction at the end of the first interrupt service routine, it pops the previously stored state information off the stack and returns to execution of the thread. Before execution of the thread resumes, however, the second interrupt causes the processor to push the state of the processor onto the stack, to disable maskable interrupts again, and to vector off to the second interrupt service routine. The processor then begins executing the second interrupt service routine.
Note that returning from the first interrupt service routine and proceeding to the second interrupt service routine causes a popping of the stack to recover state information and then immediately causes that popped state information to be pushed back onto the stack so that the second interrupt service routine can be executed. This popping and pushing performed by the conventional processor is wasteful of processing resources and slows execution of the overall program.
It is believed that a prior art processor architecture exists, where a processor executing a first interrupt service routine encounters an interrupt return instruction when a second interrupt is pending, and where the processor does not pop state information off the stack and return to the thread due to the pending second interrupt, but rather jumps to a predetermined location where an instruction is stored. The instruction is fetched, decoded and executed. Execution causes an address to be loaded into the program counter. The address is the starting address of an interrupt service routine for handling the second interrupt. After the loading of the starting address into the program counter, the processor begins execution of the interrupt service routine for the second interrupt. Unnecessary popping and pushing of the same information onto the stack is avoided, but the mechanism is cumbersome, inefficient and slow. One or more program memory locations are required to support the function. An improved mechanism is desired that reduces the amount of silicon area consumed. Not only is a faster and smaller mechanism desired, but it has also been recognized that a situation can exist where the pending second interrupt is a maskable interrupt. Software should be able to mask, or disable, maskable interrupts. If the interrupt servicing described above is practiced in a situation where the second interrupt is a maskable interrupt, then upon termination of the first interrupt routine the jumping to the second interrupt routine will cause the second interrupt routine to be executed. Even though the second interrupt was masked, the processor nonetheless will jump to its second interrupt service routine. Although software can be written to detect this situation and accommodate for it, an improved mechanism is desired that does not involve this complexity. An efficient and fast solution is desired that provides back-to-back vectoring involving maskable interrupts.